Locally clocked pipelines and dynamic logic

The SLS and RLS estimation methods proposed for average power estimation are linear, unbiased, and do not assume any distribution for the input sample data. The experimental results indicate that the least square estimation algorithms converge up to 24 times faster than the Monte Carlo and DIPE for random inputs. ACKNOWLEDGMENT The authors would like to thank the reviewers and the associate editor for their comments and suggestions. REFERENCES [1] E. M. Sentovich et al., " SIS: A system for sequential circuit synthesis, " Statistical estimation of the cumulative distribution function for power dissipation in VLSI circuits, " in Proc. Statistical estimation of average power dissipation using nonparametric techniques, " IEEE Trans. Efficient estimation of dynamic power consumption under a real delay model, " in Proc. Int. Conf. Computation of lower and upper bounds for switching activity using decision theory, " IEEE Trans. Abstract—Micropipelines and most of its variants use a delay-insensitive controller to moderate a pipeline. In search of improved performance, we depart from the delay-insensitive model in favor of a bounded-delay model for the controller. In particular, we demonstrate how a general delay-insensitive controller for level-sensitive pipelines can be improved by assuming a bounded-delay model and taking advantage of delay information to make the controller faster and more efficient. The new control scheme is referred to as locally clocked (LC) control. A highly pipelined logic technique called LC dynamic logic is presented that combines the bounded-delay controller with a latching dynamic logic gate design. Simulations comparing LC control with its delay-insensitive counterpart are presented. Also, an 8 8 bit multiplier with a maximum frequency of 715 MHz for a 1 m CMOS process that uses LC dynamic logic is presented.